Greg Waite, CEO of InventionShare, announced a new research program to be carried out by USC Viterbi School of Engineering and Susan M. Schober from the University of Southern California on how phase–locked loops (PLLs) are essential building blocks in Multi-GHz wireline and wireless integrated circuit (IC) systems in the new Circuit SeedTM invention.
The proposed study will look at the Circuit Seed designs and the challenges of scalability, low noise, low power, frequency range and stability with the goal of developing a reconfigurable multi-GHz analog PLL that is scalable and portable to and between all digital deep sub-um CMOS processes, thus reducing re-design time.
“Susan’s work will demonstrate that Circuit Seed’s design process allows for greater scalability, and the ability to reduce noise. It will look at power consumption and stability of the design process, and provide more solid research to support the claims of the invention,” said Mr. Waite.
The first steps will include restructuring the CP by viewing the circuit as a black box with Up/Down inputs, and a voltage output which may be raised or lowered via an incremental charge transfer – and then look at the new CP design which facilitates the use of an optimized no-added delay PFD with similar switching times. The last approach will be the design of a reconfigurable and scalable VCO using passive element charge injection and phase coupling to produce a tunable multi-GHZ frequency output with symmetric phases. The research will show that a seasoned team of inventors with a track record of patents on a variety of analog devices have developed revolutionary new way of processing analog signals using only digital components – and that analog signals processed with digital parts can be made at deep sub‐micron feature size.
InventionShare plans on taking the Circuit Seed invention to market by mid-2015 and will be making presentations to interested industry partners shortly.
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